New Techniques and Tools for Ensuring On-Chip Power Integrity--Down to Nanoscale
As chips continue to scale, power integrity issues are introducing unexpected project complexity and cost. In this book, two leading industry innovators thoroughly discuss the power integrity challenges that engineers face in designing at nanoscale levels, introduce new analysis and management techniques for addressing these issues, and provide breakthrough tools for hands-on problem solving.
Raj Nair and Dr. Donald Bennett first provide a complete foundational understanding of power integrity, including ULSI issues, practical aspects of power delivery, and the benefits of a total power integrity approach to optimizing chip physical designs. They introduce advanced power distribution network modeling, design, and analysis techniques that highlight abstraction and physics-based analysis, while also incorporating traditional circuit- and field-solver based approaches. They also present advanced techniques for floorplanning and power integrity management, and help designers anticipate emerging challenges associated with increased integration. Anasim RLCSim.exe, a new tool for power integrity aware floorplanning, is downloadable for free at anasim.com/category/software.
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Prentice Hall PTR
May 06, 2010
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